FIG. 4A is a block diagram showing a main portion of a solid state image pickup apparatus assembling a solid state imaging pickup device, and FIGS. 4B and 4C are schematic plan views showing the structure of the solid state image pickup device. FIG. 4D is a schematic cross sectional view showing a portion of a pixel area of a solid state pickup device.
Referring to FIG. 4A, the structure of a solid state image pickup apparatus will be described. A solid state imaging pickup device 51 generates signal charge corresponding to an amount of light incident upon each pixel and supplies an image signal corresponding to the generated signal charge. A drive signal generator 52 generates drive signals (transfer voltage, etc.) for driving the solid state image pickup device 51 and supplies them to the solid state image pickup device 51. An analog front end (AFE) 53 subjects an output signal from the solid state imaging unit 51 to correlation double sampling, amplifies the sampled signal at an externally set gain, converts it into a digital signal, and outputs the digital signal. A digital signal processor (DSP) 54 processes an image signal supplied from the analog front end 53, such as recognition process, data compression and network control, and outputs the processed image data. A timing generator (TG) 55 generates timing signals for the solid state image pickup device 51, drive signal generator 52 and analog front end 53, to control the operations thereof.
The drive signal generator 52 includes, for example, a V driver for generating a vertical charge coupled device (CCD) drive signal. Signals supplied from the drive signal generator 52 to the solid state image pickup device 51 are a horizontal CCD drive signal, a vertical CCD drive signal, an output amplifier drive signal and a substrate bias signal.
As shown in FIG. 4B, the solid state image pickup device is constituted of: a plurality of photosensors 62 disposed, for example, in a matrix shape; a plurality of vertical CCDs 64 disposed near each column of the photosensors 62; a horizontal CCD 66 electrically connected to the vertical CCDs; and an amplifier circuit 67, connected to an output terminal of the horizontal CCD 66, for amplifying an output charge signal from the horizontal CCD 66. A pixel area 61 is constituted of the photosensors 62 and vertical CCDs 64.
The photosensor 62 is constituted of a photosensitive element, e.g., a photoelectric conversion element (photodiode) and a read gate. The photoelectric conversion element generates signal charge corresponding to an incidence light amount and accumulates them. Reading the accumulated signal charge to the vertical CCD 64 is controlled by a voltage applied to the read gate. The signal charge read to the vertical CCD 64 is transferred in the vertical CCDs (vertical transfer channel) 64 toward the horizontal CCD 66 (in a vertical direction). Signal charge transferred to the bottom end of the vertical CCDs 64 is transferred in the horizontal CCD (horizontal transfer channel) 66 in a horizontal direction, amplified by the amplifier circuit 67 and output to an external.
The photosensors 62 are disposed in a tetragonal matrix layout at a constant pitch in the row and column directions as shown in FIG. 4B, or disposed in a honeycomb layout in the row and column directions by shifting every second photosensors, for example, by a half pitch.
FIG. 4C is a schematic plan view of a solid state image pickup device having the honeycomb layout. The honeycomb layout has photosensors 62 disposed in a first tetragonal matrix layout and photosensors 62 disposed in a second tetragonal matrix layout at positions between lattice points of the first tetragonal matrix layout. Vertical CCDs (vertical transfer channels) 64 are disposed in a zigzag way between photosensors 62. Although this layout is called a honeycomb layout, the photosensor 62 of most honeycomb layouts is octangular.
As shown in FIG. 4D, formed in a p-type well 82 formed in a semiconductor substrate 81, e.g., an n-type silicon substrate, are a photoelectric conversion element 71 made of an n-type impurity doped region, a p-type read gate 72 disposed next to the photoelectric conversion element, and a vertical transfer channel 73 made of an n-type region disposed next to the read gate. A p+-type burying or covering region 71a is formed on the photoelectric conversion element 71. A vertical transfer electrode 75 is formed above the vertical transfer channel 73, with a gate insulating film 74 being interposed therebetween. A p-type channel stop region 76 is formed between adjacent photoelectric conversion elements 71.
The channel stop region 76 is used for electrically isolating the photoelectric conversion elements 71, vertical transfer channels 73 and the like. The gate insulating film 74 is a silicon oxide film formed on the surface of the semiconductor substrate 81, for example, by thermal oxidation. The vertical transfer electrode 75 is constituted of first and second vertical transfer electrodes made of, for example, polysilicon. The first and second vertical transfer electrodes may be made of amorphous silicon. The potential of the vertical transfer channel 73 is controlled by a voltage (drive signal) applied to the vertical transfer electrode 75 so that signal charge is transferred in the vertical transfer channel 73. The potential of the read gate 72 is controlled by a voltage (drive signal) applied to the vertical transfer electrode 75 above the read gate 72 so that signal charge generated and accumulated in the photoelectric conversion element 71 is read to the vertical transfer channel 73. An insulating silicon oxide film 77 is formed on the vertical transfer electrode 75, for example, by thermally oxidizing polysilicon. The vertical CCD 64 is constituted of the vertical transfer channel 73, upper gate insulating film 74 and vertical transfer electrode 75.
A light shielding film 79 of, e.g., tungsten, is formed above the vertical transfer electrode 75, with the insulating silicon oxide film 77 being interposed therebetween. Openings 79a are formed through the light shielding film 79 at positions above the photoelectric conversion elements 71. A silicon nitride film 78 is formed on the light shielding film 79.
As described above, the light shielding film 79 has the openings 79a above the photoelectric conversion elements 71 and prevents light incident upon the pixel area 61 from entering the region other than the photoelectric conversion elements 71.
A planarized layer 83a made of, e.g., borophosphosilicate glass (BPSG) is formed above the light shielding film 79. On this planarized surface, a color filter layer 84 is formed which is of three primary colors: red (R), green (G) and blue (B). Another planarized layer 83b is formed on the color filter layer 84. On the planarized layer 83b having a planarized surface, micro lenses 85 are formed, for example, by melting and solidifying a photoresist pattern of micro lenses. Each micro lens 85 is a fine hemispherical convex lens disposed above each photoelectric conversion element 71. The micro lens 85 converges incidence light to the photoelectric conversion elements 71. Light converged by one micro lens 85 passes through the color filter layer 84 of one of the red (R), green (G) and blue (B) and becomes incident upon one photoelectric conversion element 71. Therefore, the photoelectric conversion elements include three types of photoelectric conversion elements: photoelectric conversion elements upon which light passed through the red (R) color filter layer 84 becomes incident; photoelectric conversion elements upon which light passed through the green (G) color filter layer 84 becomes incident; and photoelectric conversion elements upon which light passed through the blue (B) color filter layer 84 becomes incident.
FIGS. 5A and 5B are schematic diagrams illustrating a manufacture method for a solid state image pickup device.
Referring to FIG. 5A, a semiconductor substrate 81, e.g., an n-type silicon substrate, is prepared and p-type impurities, e.g., boron ions, are implanted to form a p-type well 82.
In a surface layer of the well 82, n-type impurities, e.g., phosphorus or arsenic ions, are implanted to form a vertical transfer channel 73. A read gate 72 and a channel stop region 76 are formed by implanting p-type impurities, e.g., boron ions. An insulating film 74 is formed on the semiconductor substrate 81, the insulating film being an oxide-nitride-oxide (ONO) film including a thermally oxidized silicon oxide film, a silicon nitride film formed through chemical vapor deposition (CVD) and a silicon oxide film formed by thermally oxidizing the surface of the silicon nitride film.
A vertical transfer electrode 75 made of, for example, polysilicon, is formed covering the vertical transfer channel 73. The vertical transfer electrode 75 is made of, for example, first and second transfer electrodes stacked in the vertical direction. The vertical transfer electrode 75 is formed by depositing polysilicon on the insulating film 74, for example, by CVD and patterning it through photolithography and etching.
By using the vertical transfer electrode 75 as a mask or by using a resist pattern formed by coating resist on the surfaces of the vertical transfer electrode 75 and insulating film 74 and exposing and developing the resist, n-type impurities, e.g., phosphorus or arsenic ions are implanted to form a photoelectric conversion element 71. A burying layer 71a is formed by implanting p-type impurities, e.g., boron ions. The vertical transfer electrode 75 is thermally oxidized to form a silicon oxide film 77 on the surface thereof.
A horizontal CCD 66 is also formed in the semiconductor substrate 81 by using the above-described processes. An amplifier circuit 67 and the like are also formed.
Referring to FIG. 5B, a light shielding film 79 of, for example, tungsten, is formed above the silicon oxide film 77. Resist is coated on the light shielding film 79, exposed and developed to leave the resist in predetermined areas. By using this resist as a mask, the light shielding film 79 is etched to form an opening 79a above the photoelectric conversion element 71.
A silicon nitride film 78 is formed covering the light shielding film 79, and then a planarized layer 83a of BPSG is formed, for example, by CVD. For example, a deposited BPSG film is reflowed at 850° C. to form the planarized layer 83a. In addition to reflow, planarization may be performed, for example, by chemical mechanical polishing (CMP). Instead of BPSG, silicon oxide doped with impurities to lower a melting point may also be used.
On the planarized surface of the planarized layer 83a, a color filter layer 84 of three primary colors of red (R), green (G) and blue (B) is formed. For example, the color film layer 84 is formed by coating photoresist liquid mixed with granular pigment (pigment dispersed resist liquid) on the surface of the planarized layer 83a, exposing and developing it and curing it at a curing temperature of 220° C. Filter layers of three colors of red (R), green (G) and blue (B) are sequentially formed.
A planarized layer 83b is formed on the color filter layer 84 because the surface of the color filter layer 84 is irregular. For example, the planarized layer 83b is formed by coating material having the similar composition as that of transparent resin and curing it at a curing temperature of 220° C. Next, micro lenses 85 are formed on the planarized layer 83b. 
FIGS. 6A and 6B are schematic cross sectional views showing the insulating film 74 near the read gate 72.
Referring to FIG. 6A, the insulating film 74 often adopts the ONO structure having the silicon nitride film 74b as an oxygen intercepting film sandwiched between the silicon oxide films 74a and 74c, as described earlier. Electrons constituting signal charge are accelerated by an electric field generated by a read voltage and partially become hot electrons, which may be trapped at the interface between the silicon nitride film 74b and silicon oxide film 74a, which may induce a temporal change in the read voltage.
The invention aiming to provide a solid state image pickup device is disclosed which device is stable, highly reliable, thin, and high in breakdown voltage and can suppress a temporal change in the read voltage caused by hot electrons (e.g., refer to Japanese Patent Laid-open Publication No. 2003-332556).
FIG. 6B is a schematic cross sectional view showing a characteristic portion of a solid state image pickup device according to the invention described in Japanese Patent Laid-open Publication No. 2003-332556. As shown, the solid state image pickup device of this invention includes a photoelectric conversion element 71 formed in a semiconductor substrate 81 and an insulating film 74 above a vertical transfer channel 73 near the photoelectric conversion element. The insulating film 74 has a lamination structure of silicon oxide films 74a and 74c and a silicon nitride film 74b. At least the silicon nitride film 74b of the insulating film 74 does not extend near to the upper end portion of the photoelectric conversion element 71.
FIGS. 7A to 7E are schematic cross sectional views illustrating a manufacture method for the characteristic portion of the solid state image pickup device according to the invention described in Japanese Patent Laid-open Publication No. 2003-332556.
Referring to FIG. 7A, on the surface of a p-type well 82 formed in a semiconductor substrate 81 of an n-type silicon substrate, an insulating film is formed having a three-layer structure of a silicon oxide film 74a having a thickness of 15 nm, a silicon nitride film 74b having a thickness of 50 nm and a silicon oxide film 74c having a thickness of 10 nm sequentially formed in this order from the bottom. Next, a heavily doped polysilicon film having a thickness of 0.4 μm is formed in order to form a vertical transfer electrode 30.
As shown in FIG. 7B, by using a resist pattern formed through photolithography as a mask, the polysilicon film is patterned by reactive ion etching (RIE) to form the electrode 30. By using the electrode 30 as a mask, the silicon oxide film 74c is etched.
As shown in FIG. 7C, a thermally oxidized film 31 is formed on the surface of the electrode 30 through thermal oxidation. The thermally oxidized film 31 is hardly formed on the silicon nitride film 74b. The thermally oxidized film 31 on the silicon nitride film 74b, if any, can be removed easily by an acid process.
As shown in FIG. 7D, after the thermally oxidized film 31 on the silicon nitride film 74b is removed by an acid process, the silicon nitride film 74b is selectively wet-etched with hot phosphoric acid, being laterally etched by a width of about 0.2 μm under the end portion of the electrode 30.
As shown in FIG. 7E, thermal oxidation is performed to bury the region under the end portion of the electrode without the silicon nitride film 74b. 
In the solid state image pickup device formed in this manner, the insulating film under the electrode 30 near the photoelectric conversion element 71 has at its end portion a single layer structure of the silicon oxide film not containing the silicon nitride film 74b. It is therefore possible to maintain good read characteristics without a temporal change in the read voltage.
This single layer structure can be formed through isotropical etching without the necessity of a new photolithography process. A solid state image pickup device having good characteristics can be manufactured very easily with good workability.